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  Conference Program
October 8, 2013
Session 1: Opening Session
Chairperson: E. Kondoh
9:30-9:50 Opening Remarks: J. Koike, Chair of Asian Session [Tohoku Univ.]
Award Ceremony : F. Ito [Toshiba]
Keynotes: Aiming at Voltage Reduction of Devices for Low -power Electronics [LEAP] S. Kimura
Keynotes: Flash Memory Technology For the Zetabyte Era [SanDisk (Japan) ] A. Koike
Session 2: Process Integration
Chairperson: K. Maekawa
Invited: Advanced Metallization Concepts and Impact on Reliability [Globalfoundaries] M. Hauschildt, B. Hintze, M. Gall, F. Koschinsky, A. Preusse, T. Bolom, O. Aubel, G. Talut, and E. Zschech
Improvement of Cu gap-fill performance for isolation pattern [Renesas Electronics] A. Nakajima, Y. Yamamoto, T. Nakamura, and T. Usami
Reflow behavior of Cu -Mn in LSI line patterns [Tohoku Univ.] T. Saito, D. Ando, Y. Sutou, and J. Koike
12:20-13:30 (Lunch Break)
Session 3: Low-k
Chairpersons: T. Nemoto
Invited: Low-k Dielectric Chip Package Interaction and Mechanical Reliability [IBM] Xiao Hu Liu, T.M. Shaw, and G. Bonilla
Invited: Plasma-enchanced ALD Dielectric Barrier for Extending Low-k Scaling < 2.3 [ASM Japan] N. Kobayashi, A. Kobayashi, A. Nakano, D. Ishikawa, and K. Matsushita
The Use of Monoenergetic Positron Beams for Characterizing the Porosity of Complex Stacks of Porous Low-k with ALD Metal Films [1Univ. of Tsukuba, 2IMEC, 3AIST] A. Uedono1, P. Verdonck2, A. Delabie2, J.Swerts2, T.Witters2, T. Conard2, M. R. Baklanov2, S. V. Elshocht2, N. Oshima3, and R. Suzuki3
14:50-15:00 (Break 10 min)
Session 4: Nanocarbon
Chairperson: T. Sakai / S. Noda / S. Sato / K. Ueno
Invited: Prospects of Nano Carbons and Emerging 2D-Crystals for Next-Generation Green Electronics [UCSB] K. Banerjee
Transfer Process and Contact Resistance of Multilayer Graphene Wires on Tungsten Plugs for Local Interconnects [AIST] M. Sato, M. Takahashi, M. Nihei, S. Sato, and N. Yokoyama
Characterization of 10-layer Graphene Interconnects Fabricated by 10-time Transfer of Single-layer CVD-grown Graphene [AIST] H. Nakano, D. Kondo, B. Zhou, K. Hayashi, K. Yagi, M. Takahashi, M. Sato, S. Sato, and N. Yokoyama
16:10-16:20 (Break 10 min)
Invited: Growth and Integration of Graphene and CNT for 3D Interconnect Applications [LEAP] T. Sakai, Y. Yamazaki, T. Matsumoto, D. Nishide, M. Kitamura, M. Wada, T. Ishikura, T. Saito, M. Katagiri, H. Miyazaki, M. Suzuki, L. Zhang, A. Isobayashi, A. Sakata, M. Watanabe, N. Sakuma, and A. Kajita
Bromine Doping of Multilayer Graphene for Low Resistance Interconnects [1Shibaura Institute of Technology, 2LEAP] R. Kosugi1, K. Imazeki1, A. Aozasa1, Y. Matsumoto1, H. Miyazaki2, N. Sakuma2, A. Kajita2, T. Sakai2, and K. Ueno1
Direct Synthesis of Graphene on Dielectric Substrates by "etching-precipitation" Method [1Univ. of Tokyo, 2Waseda Univ.] M. Kosaka1,2, S. Takano1, and S. Noda2
Multilayer Graphene Grown by Chemical Vapor Deposition at Low Temperatures for Interconnect Applications [LEAP] M. Katagiri, H. Miyazaki, Y. Yamazaki, L. Zhang, T. Matsumoto, M. Wada, A. Kajita, and T. Sakai
October 9, 2013
Session 5: Advanced Metal Processes
Chairperson: M. B. Takeyama / N. Hata
Invited: Fabrication of High-Quality and Reliability Cu Interconnects by Chemical Processes [Univ. of Tokyo] Y. Shimogaki, H. Kim, H. Shimizu, K. Shima, and T. Momose
Cu Coating Inside Ultra High-aspect-ratio (>130) and Bended Through-hole Using Supercritical CO2 Fluid [1Univ. of Yamanashi, 2Fujikura] M. Watanabe1, Y. Takeuchi1, T. Ueno1, M. Matsubara1, E. Kondoh1, S. Yamamoto2, N. Kikukawa2, and T.Suemasu2
Step Coverage Analysis on Nickel Thin Films by Hot-wire-assisted ALD [Univ. of Tokyo] G. Yuan, H. Shimizu, T. Momose, and Y. Shimogaki
10:10-10:30 (Break 20 min)
Invited: Interface adhesion energy and apparent adhesion strength between Cu and insulation layers in damascene metallization systems [Nagoya Inst. of Tech., JST] S. Kamiya
Room-temperature Intermixing at Cu/SiO2 Interface in Reliable Metallization by Adopting SiO2 Surface Dope and Noble Metal Catalyzation [Univ. of Yamanashi] M. Watanabe, A. Teraoka, and E. Kondoh
Processing and Characterization of Co-Sn Compound [1Tokyo Institute of Technology, 2IMEC, 3Intel] M. O1, G. Vakanas2,3, B. Dimcic2, and M. Kajihara1
Adsorption Behavior of Poly (Ethylene Glycol) in the Presence of Different Kinds of Halide Ions with a Microfluidic Device and an EQCM [Osaka Pref. Univ.] Y. Tsujimoto, Y. Miyamoto, N. Okamoto, T. Saito, and K. Kondo
12:00-13:30 (Lunch Break)
Session 6: Reliability and Contacts
Chairperson: O. Nakatsuka / S. Yokogawa
Invited: Voltage, Temperature and Area Scaling of Low-k TDDB [1IBM, 2Globalfoundaries] F. Chen1, K. Y. Yiang2, M. Shinosky1, and C. Graas1
Lifetime Prediction Model for Stress-induced Voiding in Cu/low-k Interconnects [Polytechnic Univ.] S. Yokogawa
Measurement of Specific Contact Resistivity by Refined Transmission Line Method [Tohoku Univ.] B. T. Bae, D. Ando, Y. Sutou, and J. Koike
Formation and Crystalline Structure of Ni Silicides on Si(110) Substrate [Nagoya Univ.] O. Nakatsuka, M. Hasegawa, K. Kato, N. Taoka, and S. Zaima
Thermal Stability of Epitaxial NiGe Layers Formed on Ge(110) Substrate [Nagoya Univ.] D. Yunsheng, O. Nakatsuka, N. Taoka, and S. Zaima
15:20-15:30 (Break 10 min)
Poster Session (15:30-17:00)
Chairperson: E. Kondoh
P-1 Formation of Mn Barrier Layer on Porous SiOC by Chemical Vapor Deposition [1Tohoku Univ., 2Ube Industries] Y. Tsuchiya1, Y. Sutou1, J. Koike1, H. Kanato2, and K. Watanuki2
P-2 Area-Selective Chemical Vapor Deposition of Co as a Capping Layer for Cu Interconnect [1Yonsei Univ.] J. Yoon1, B. Jo2, and H. Kim1
P-3 Atomic Layer Deposition of Ruthenium Thin Films Using Isopropylmethylbenzene-cyclohexadiene-ruthenium and N2/H2 Plasma as a Seed Layer for Cu Electroplating [1Korea Basic Science Institute, 2Yeungnam University, 3Daegu Gyeongbuk Institute of Science & Technology, 4University of Ulsan] T. E. Hong1, K.-Y. Mun2, S.-H. Kim2, T. Cheon2, 3, B.-Y. Lim4, and S. Kim4
P-4 Cu Filling of 10-nm Trenches by High-magnetic-field Magnetron Sputtering [Tokyo Univ. of Science] M. Itoh, Y. Uhara, and S. Saito
P-5 Deposition of Cu-Ni Alloy Thin Films in Supercritical Carbon Dioxide Solutions [Univ. of Yamanashi] M. Rasadujjaman, M. Watanabe, and E. Kondoh
P-6 A New Cu(ReTaNx ) Copper Alloy Film for Making Copper Interconnects [Asia-Pacific Institute of Creativity] C.H.Lin
P-7 Growth and Diffusion Barrier Properties of CVD Mn Oxide in a TSV Structure [Tohoku Univ.] H. Wang, Y. Sutou, J. Koike, K. Lee, J. Bea, M. Murugesan, T. Fukushima, T. Tanaka and M. Koyanagi
P-8 Study of Via Filling Capability of Sn Plating [JCU] M. Hori,T. Sato,M. Matsumoto,K. Tokio,and T. Fukushima
P-9 Characterization of SiNx Film as Insulating Barrier Applicable to TSV [1Kitami Institute of Technology, 2Fujitsu Laboratories] M. B. Takeyama1, M. Sato1, Y. Kobayashi2, Y. Nakata2, T. Nakamura2, and A. Noya1
P-10 Fabrication of Copper/Single-Walled Carbon Nanotube Composite Films via Electroless Plating [Shinshu Univ.] T. Osaki, and S. Arai
P-11 Growth of High-density Carbon Nanotube Arrays on Conductive Underlayers at 400 °C Toward via Interconnects in ULSIs [1Univ. of Tokyo, 2Waseda Univ.] N. Na1,2, Y.-G. So1, Y. Ikuhara1, and S. Noda2
P-12 Study on Sapphire CMP Using Fullerenol Mixed Slurry - Effect on the Size of Silica and Diamond Fine Particles- [1Kyushu Institute of Tech., 2National Taiwan Univ. of Sci. and Tech] K. Suzuki1, S. Kawakita1, P. Khajornrungruang1, and K. Kimura1,2
P-13 GeSn Film Deposition Using Metal Organic Precursors [1Meiji Univ., 2Gas-phase Growth, 3Toyota Technological Institute] K. Suda1, S. Ishihara1, H. Machida2, M. Ishikawa2, H. Sudoh2, Y. Ohshita3, and A. Ogura1
P-14 Temperature Dependence of Resistance of Conductive Nano-filament Formed in Ni/NiOx/Pt ReRAM [Kansai Univ.] S. Otsuka, Y. Hamada, T. Shimizu, and S. Shingubara
17:00-17:20 (Break 20 min)
Sponserd Banquet (17:20-18:50)
October 10, 2013
Session 7: Backend Device Technologies
Chairperson: M. Tada / C. S. Hwang
Invited: Atomic Layer Deposition and chemical Vapor Deposition of Ru, RuO2, and SrRuO3 [Seoul National Univ.] C. S. Hwang
Invited: Mixed Ionic Electronic Conduction (MIEC) Based Access Devices for 3-D Multi-layer Crosspoint Memory [IBM] K. Virwani, G. W. Burr, R. S. Shenoy, G. Ho, C. T. Rettner, A. Padilla, R. S. King, K. Nguyen, A. N. Bowers, M. Jurich, M. BrightSky, E. A. Joseph, A. J. Kellock, N. Arellano, B. N. Kurdi, and K. Gopalakrishnan
A Wafer Warpage Reduction by Material Property Control and Cu-RDL Design Optimization for Wafer-level White LED Package [Toshiba] H. Tomizawa, A. Kojima, M. Shimada, Y. Akimoto, M. Shimojuku, H. Furuyama, Y. Sugizaki and H. Shibata
10:20-10:40 (Break 20 min)
Invited: A Novel MTJ for Embedded STT-MRAM with a Dummy Free Layer and Dual Tunnel Junctions [LEAP] K. Tsunoda, H. Noshiro, C. Yoshida, Y. Yamazaki, A. Takahashi, Y. Iba, A. Hatada, M. Nakabayashi, T. Takenaga, M. Aoki, and T. Sugii
Phase Transition Characteristics of GeCu2Te3 Film for PCRAM [1Tohoku Univ, 2AIST] Y. Sutou1, Y. Saito2, and J. Koike1
A Phase Change Memory Using Confined GeTe/Sb2Te3 Superlattice Deposited by Chemical Vapor Deposition [LEAP] T. Morikawa, M. Kitamura, T. Ohyanagi, M. Tai, M. Kinoshita, K. Akita, and N. Takaura
Aluminum - doped Zinc Oxide Electrodes for PbLaZrTiOx capacitors [1Osaka Pref. Univ., 2Osaka Univ.] Y. Takada1, T. Tsuji1, N. Okamoto1, T. Saito1, K. Kondo1, T. Yoshimura1, N. Fujimura1, K. Higuchi2, A. Kitajima2, and A. Oshima2
12:10-13:20 (Lunch Break)
Session 8: Chemical Mechanical Polishing
Chairperson: S. Kondo / Y. Yamada
Invited: FEOL 300-mm Roadmap; Challenges and Successes [Intel] J. Sorooshian
Invited: The Role of CMP Technologies for Embedded Memories [Renesas Electronics] T. Taiji
Identification of Nonlinear Viscoelasticity of CMP Pads [Nagoya Univ.] N. Suzuki, A. Kato, M. Asaba, and E. Shamoto
Study on Variable Rotation Polishing Method in CMP Process - Influence of the Asperity on Polishing Pad to Increase Material Removal Rate - [1Kyushu Institute of Tech., 2National Taiwan Univ. of Sci. and Tech.] P. Phaisalpanumas1, K. Suzuki1, K. Kimura1,2 and P. Khajornrungruang1
15:00-15:20 (Break 20 min)
Session 9: 3D challenges
Chairpersons: T. Ohoba / T. Saito
Invited: 3DIC Integration Technology and Challenge [ITRI] T.K. Ku, C. H. Lin, P. J. Tzeng, E. H. Chen, T. C. Hsu, S. C. Chen, C. C. Wang, J. C. Chen, C. C. Chen, Y. C. Hsin, S. C. Liao, P. C. Chang, Y. M. Lin, and Y. H. Chang
Invited: 3D Challenges - Low Temperature Bonding using Surface Activation Processes [Univ. of Tokyo] T. Suga
Impact of Back Grind Damage on Si Wafer Thinning for 3D Integration [1Fujitsu Laboratories, 2Tokyo Institute of Technology, 3Disco, 4Toray Research Center, 5Univ. of Tsukuba] Y. Mizushima1,2, Y. Kim2,3, T. Nakamura1, R. Sugie4, H. Hashimoto4, A. Uedono5, and T. Ohba2
Development of Bumpless COW Using <20 μm Thick 1 Gbit DDR3 SDRAM for Tera-Scale Application [1Tokyo Institute of Technology, 2DISCO, 3Dai Nippon Printing, 4Fujitsu Laboratories] N. Maeda1, H. Kitada1, K. Fujimoto3, Y. S. Kim1, S. Kodama2, S. Yoshimi3, Y. Mizushima4, K. Masu1, and T. Ohba1
Fluctuation of Lattice Spacing around Trough Si Vias in Wafer -on -wafer Structures [1Nagoya Unv., 2Fujitsu Laboratories, 3Tokyo Institute of Technology, 4Univ. of Tokyo] N. Taoka1, O. Nakatsuka1, Y. Mizushima2,3, H. Kitada2,3, Y. S. Kim3,4, T. Nakamura2, T. Ohba 3,4 , and S. Zaima1
A Novel TSV Exposure Process Comprising Si/Cu Grinding, Electroless Ni-B Plating, and Wet Etching of Si [1AIST, 2Apprecia Technology, 3Okamoto Machine Tool Works] N. Watanabe1, M. Aoyagi1, D, Katagawa2, T. Bandoh3, and E. Yamamoto3
17:40-17:50 Closing Remarks: E. Kondoh [Yamanashi Univ.]
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