| October 20, 2009 |
Session 1: Opening Session
Chairperson: S. Kondo |
9:30
-9:40 |
Opening Remarks: Y. Shimogaki, Chair of Asian Session [The
Univ. of Tokyo]
Award Ceremony |
9:40
-10:20
(1-1) |
Keynotes: Be The World's No.1 [Elpida Memory] Y. Sakamoto |
10:20
-11:00
(1-2) |
Keynotes: Enabling 3D - process technologies for devices,
interconnect and packaging [Applied Materials]
H. Stork |
Session 2: Wet Process/Corrosion
Chairperson: S. Kondo |
11:00
-11:30
(2-1) |
Invited: Application of High-Productivity Combinatorial(HPC)
Technology to Cu/Low-k Process [Intermolecular]
D. Lazovsky |
11:30
-11:50
(2-2) |
Effect of Pattern Layout and Dissolved Oxygen
in CO2 Rinse Water on Cu Corrosion during
Post-Etch Cleaning [Semiconductor Leading
Edge Technologies, *Organo] K.Tokuri Yamashita*,
M. Shiohara, N. Oda, S. Kondo, and S. Saito |
11:50
-12:10
(2-3) |
A Study of Photo Corrosion with Photodiode
and Quartz Crystal Microbalance [Ebara] S.
Shima, Y. Wada, K. Tokushige, A. Fukunaga,
and M. Tsujimura |
| (Lunch 1hour 20min) |
Session 3: Low-k Dielectrics
Chairpersons: Y. Uchida, T. Kokubo |
13:30
-14:00
(3-1) |
Invited: Integration of Photo-Patternable Low-K Materials
into Advanced Cu BEOL [IBM] Q. Lin |
14:00
-14:20
(3-2) |
Novel precursor for development of Si-C2H4-Si
networks in SiCH for application as a low-k
cap layer beyond the 22 nm node [Taiyo-Nippon
Sanso, *National Institute for Material Science,
**Tri Chemical Laboratories] H. Shimizu,
*N. Tajima, **T. Kada, S. Nagano, Y. Ohashi,
and S.Hasaka |
14:20
-14:40
(3-3) |
Integration of porogen-based low-k films:
influence of capping layer thickness and
long thermal anneals on low-k damage and
reliability [ASM Belgium, *IMEC, **ASM Japan]
D. De Roest, B. Vereecke*, C. Huffman*, N.
Heylen*, K. Croes*, H. Arai**, N. Takamure**,
J. Beynet, H.Sprey, K. Matsushita**, N. Kobayashi**,
P. Verdonck*, S. Demuynck*, G. Beyer*, Z.
Tokei* |
14:40
-15:00
(3-4) |
Characterization of damage in Low-k side
walls by micro beam IR method [Toray Research
Center] H. Seki, T. Matsunobe, H. Hashimoto |
15:00
-15:20
(3-5) |
Trench Sidewall Elimination Effect on Line-to-Line
Leakage Current in Scalable Porous Silica
(k = 2.1)/Cu Interconnect Structure [Semiconductor
Leading Edge Technologies] A. Gawase, S.
Chikaki, N. Nakamura, E. Soda, N. Oda, and
S. Saito |
15:20
-15:40
(3-6) |
Cu/low-k Interconnects for 32nm-node and
beyond with High Etching-selective [Semiconductor
Leading Edge Technologies, *Taiyo Nippon
Sanso] J. Nakahira, S. Nagano*, A. Gawase,
Y. Ohashi*, H. Shimizu*, S. Chikaki, N. Oda,
S. Kondo, S. Hasaka*, and S. Saito |
| (Coffee Break 20min) |
Session 4: CMP
Chairperson: D. L. Diehl |
16:00
-16:30
(4-1) |
Invited: Kinetic and Tribological Fundamentals of
CMP processes [The Univ. of Arizona] A.Philipossian |
16:30
-16:50
(4-2) |
Cu Dual-Damascene Interconnects with Direct-CMP
process on porous low-k Film [Renesas Technology]
J. Izumitani, D. Kodama, S. Kido, H. Chibahara,
Y. Oka, K. Goto, N. Suzumura, M. Fujisawa,
and H. Miyatake |
16:50
-17:10
(4-3) |
Hybrid e-CMP/CMP Process for Cu Dual Damascene
TSV Interconnects by Using Non-Contact Electrode
e-CMP Pad [Roki Techno, *The Univ. of Tokyo]
D. Abe, T. Enomoto, S. Tominaga, H. Kitada*,
and T. Ohba* |
Session 5: New Interconnect Technologies
Chairperson: K. Asai |
17:10
-17:40
(5-1) |
Invited: Novel Printing Process of Organic TFT Backplane
for Flexible Electronic Paper [Ricoh] K.
Suzuki, K. Yutani, A. Onodera, T. Tano, H.
Tomono, A. Murakami, M.Yanagisawa, K. Kameyama,
and I. Kawashima |
17:40
-18:00
(5-2) |
Amorphous Carbon Hard Mask for 45nm Contact
Patterning [Chartered Semiconductor Manufacturing,
*Applied Materials South East Asia] X. S.
Rao, J. Widodo, W. Lu , M. S. Zhou, L. C.
Hsia, T. Chu*, R. K. H. Lee*, A. Jain*, H.
Yu*, B. T. Nguyen*, and D. Padhi * |
18:00
-18:20
(5-3) |
MEMS inductor configurations with shields
for achieving large inductance variations
[Tokyo Institute of Technology] Y. Mizuochi,
S.Amakawa, N. Ishihara, and K. Masu |
18:20
-18:40 |
Guest Paper from AMC USA: Stefan E. Schulz (Chemnitz Univ. of Technology) |
Session 6: Poster Session & Banquet (18:40-20:30)
Chairperson: K. Ueno |
| Low-k/Dielectrics |
| (P-1) |
Photoinduced Leakage Current in SiCN Dielectrics
for Copper Diffusion Barriers [Tokai Univ.]
T. Ide, and K. Kobayashi |
| (P-2) |
Proposal of New Precursors for PECVD SiOCH
Low-k films with Plasma Damage Resistance
[Taiyo-Nippon Sanso, *National Institute
for Material Science, **Tri Chemical Laboratories]
Y. Ohashi, N. Tajima*, Y. Xu**, T. Kada**,
S. Nagano, H. Shimizu, and S. Hasaka |
| (P-3) |
Penetration Characteristics of ALD-TiN to
1nm-pore Low-k SOD Films [ULVAC] M. Hirakawa,
T. Yamazaki, I. Tojo, T. Nakayama, and H.
Murakami |
| (P-4) |
Determinant of Electrical Leakage Current
for porous SiOC film [ASM Japan] K. Matsushita,
A. Nakano, I. Yanagisawa, Y. Nonaka, and
N. Kobayashi |
| (P-5) |
UV-cured silicon nitride stress modulation
[Chartered Semiconductor Manufacturing] J.
Z. Tian, B. Zuo, W. Lu, M. S. Zhou, L. C.
Hsia |
| (P-6) |
SACVD O3-TEOS Process for STI Gap-Fill [Chartered
Semiconductor Manufacturing] X. S. Rao, B.
Zuo, W. Lu, M. S. Zhou, and L. C. Hsia |
| (P-7) |
An Effective Approach for Developing Nitrogen
Doped Silicon Carbide Dielectric Diffusion
Barrier Films for Improved Device Reliability
in Metal HM Low-k BEOL Integration [Novellus
Systems International, *Novellus Systems,
**United Microelectronics Corporaiton] L.
L. Soh, A. Banerji*, W. Graff, G. Jiang*,
M. Sriram*, H.-J. Wu*, H. C. Fang**, S. W.
Liau**, Y. H. Liu** |
| Metal gate/Silicide/others |
| (P-8) |
Formation of Palladium Silicide on Heavily
Doped Si (001) Substrates Using Ti Intermediate
Layer [Nagoya Univ.] R. Suryana, O. Nakatsuka,
and S. Zaima |
| (P-9) |
Low Temperature Plasma-Enhanced Atomic Layer
Deposition Co [Pohang Univ. of Science and
Technology, *Air Liquide US, **Air Liquide
Laboratories] J.-M. Kim, H.-B.-R. Lee, C.
Lansalot*, C. Dussarrat*, J. Gatineau**,
and H. Kim |
| (P-10) |
Plasma-Enhanced Atomic Layer Deposition of
Ni [Pohang Univ. of Science and Technology,
*Korea Research Institute of Chemical Technology]
H.-B.-R. Lee, S. H. Bang, G. H. Gu, Y. K.
Lee*, T.-M. Chung*, C. G. Kim*, C. G. Park,
and H. Kim |
| (P-11) |
GeSbTe-thin film formation by CVD for next
generation memory (PCRAM: Phase Change RAM)
materials [Gas-phase Growth, *The Univ. of
Tokyo, **Meiji Univ., Toyota Technological
Institute] H. Machida,*, S. Hamada**, T.
Horiike**, M. Ishikawa,*,**, A. Ogura**,
Y. Ohshita***, and T. Ohba** |
| Barrier metal |
| (P-12) |
Failure Mechanism of Extremely Thin VN barrier
between Cu and SiO2 [Kitami Institute of
Technology] M. B. Takeyama, T. Itoi, and
A. Noya |
| (P-13) |
Reactively Sputtered Nanocrystalline ZrN
Film as Extremely Thin Diffusion Barrier
between Cu and SiO2 [Kitami Institute of
Technology] M. B. Takeyama, M. Sato, and
A. Noya |
| (P-14) |
Alloying effect on interfacial toughness
of Cu/TaN interface [The Univ. of Tokyo]
S. Ikemoto, S. Nambu, J. Inoue, and T. Koseki |
| Cu deposition |
| (P-15) |
Enhanced Grain Growth of Electroplated Copper
Film by Annealing in Super-Critital CO2 with
H2 [Shibaura Institute of Technology, *KISCO,
**Toray Research Center] Y. Shimada, S. Yomogida*,
S. Akahori**, T. Yamamoto**, T. Yamaguchi,
K. Aoki, A. Matsuyama*, T. Yata*, H. Hashimoto**,
and K. Ueno |
| (P-16) |
Initial Cu growth in Cu-seeded and Ru-lined
narrow trenches for supercritical fluid Cu
chemical deposition [Univ. of Yamanashi]
E. Kondoh, M. Matsubara, and K. Tamai |
| CMP |
| (P-17) |
Fundamental Study on CMP Slurry of Cobalt
Barrier Metal for Next Generation Process
[Nitta haas] H. Nishizawa, H. Nojo, and A.
Isobe |
| (P-18) |
Evaluation of Cu-CMP slurry performance using
CMP TEG wafer [Consortium for Advanced Semiconductor
Materials and Related Technologies] K. Okutani,
Y. Ootsuki, T. Tanaka, and Y. Kawamoto |
| TSV/Package |
| (P-19) |
Stress Analysis for Chip-Package Interaction
of Cu/Low-k Multi-layer Interconnects [Hitachi,
*Renesas Technology] Y. Kumagai, H. Ohta,
M. Fujisawa*, T. Iwamoto*, and A. Ohsaki* |
| (P-20) |
Perfect conformal electroless plating of
barrier and Cu for TSV [Kansai Univ. *National
Institute of Information and Communications
Technology] T. Yokoyama, F. Inoue, K. Yamamoto*,
S. Tanaka*, and S. Shingubara |
| (P-21) |
Wafer Level Alignment Accompanied With Wafer
Stacking for wafer-on-a-wafer (WOW ) Technology
using Polymer Adhesive [Dai Nippon Printing,
* Nissan Chemical Industries, ** The Univ.
of Tokyo] K. Fujimoto, M. Akazawa, H. Uehara*,
J. Katayama* , N. Maeda**, H. Kitada**, K.
Suzuki, and T. Ohba** |
| (P-22) |
Development of Permanent Bonding Material
for 3DI Process [Nissan Chemical Industries,
*Dai Nippon Printing, **The Univ. of Tokyo]
H. Uehara, J. Katayama*, K. Fujimoto*, N.
Maeda**, H. Kitada**, K. Suzuki*, and T.
Ohba** |
| October 21, 2009 |
Session 7: Cu Deposition
Chairpersons: J. Koike, O. Nakatsuka |
9:00
-9:30
(7-1) |
Invited: Copper Films Grown via Copper Oxide ALD:
Routes and Challenges for Integration into
Next-Generation Interconnects [Chemnitz Univ.
of Technology] S.E. Schulz, T. Waechtler,
L. Hofmann |
9:30
-9:50
(7-2) |
An optimization of dual-damascene through
silicon via (DD-TSV) copper plug using ECP-Cu
and e-CMP for Wafer-on-a-Wafer (WOW) technology
[Dai Nippon Printing, *Roki Techno, **The
Univ. of Tokyo] Y. Hitomi, K. Fujimoto, S.
Tominaga* ,H. Kitada**, and T. Ohba** |
9:50
-10:10
(7-3) |
The step coverage quality of Cu film by SCFD
compared with CVD [The Univ. of Tokyo] T.
Momose, M. Sugiyama, and Y. Shimogaki |
10:10
-10:30
(7-4) |
Copper Electroplating Process for Via Filling
in 3D Packaging [Ebara] M. Nagai, M. Simoyama,
Y. Tamari, M. Tanaka, N. Saito, and F. Kuriyama |
| (Coffee Break 20min) |
Session 8: Contact/Silicide
Chairpersons: O. Nakatsuka, J. Koike |
10:50
-11:20
(8-1) |
Invited: Contact Technology for Nano-Scaled CMOS [Nagoya
Univ.] S. Zaima |
11:20
-11:40
(8-2) |
Atomic Layer Deposition of Nickel Thin Films
and Application to Area Selective Deposition
[Pohang Univ. of Science and Technology s,
*Seoul National Univ.] W.-H. Kim, H.-B.-R.
Lee, K. Heo*, S. Hong*, and H. Kim |
11:40
-12:00
(8-3) |
Tungsten Contact and Line Resistance Reduction
with advanced Pulsed Nucleation Layer (PNL)
and Low Resistivity Tungsten (LRW) treatment
[Novellus Systems, *NEC Electronics, **Novellus
Systems Japan] A.Chandrashekar, F. Chen,
J. Lin, R. Humayun, P. Wongsenakhum, S. Chang,
M. Danek, E. Klawuhn, T. Itou*, T. Nakayama*,
A. Kariya*, M. Kawaguchi**, S. Hizume** |
| (Lunch 1hour 20min) |
Session 9: Cu/Barrier Depostion
Chairpersons: M. B. Takeyama, E. Kondoh |
13:20
-13:40
(9-1) |
Restraint of Copper Oxidation using Barrier
Restoration Technique with Cu-Mn alloy [Fujitsu
Microelectronics] M. Haneda, N. Ohtsuka,
H. Kudo, T. Tabira, M. Sunayama, N. Shimizu,
H. Ochimizu, and A.Tsukune |
13:40
-14:00
(9-2) |
Advanced Barrierless Metallization for Cu
Interconnect Applications [Chin-Min Institute
of Technology, *National Taiwan Univ. of
Science and Technology, **National Taiwan
Ocean Univ.] C. H. Lin , J. P. Chu* , W.
K. Leau**, and D. Y. Yu** |
14:00
-14:20
(9-3) |
Diffusion barrier properties of 10 nm RuW
alloy for advanced Cu Metallization [National
Cheng Kung Univ., *United Microelectronics
Corporaiton] J.-B.Yeh, D.-C. Perng, K.-C.
Hsu, and C. Huang* |
14:20
-14:40
(9-4) |
Effects of Water Desorption from Dielectric
Substrates on the Thickness of the CVD-MnO
Diffusion Barrier Layer [Tokyo Electron,
*Tohoku Univ.] K. Matsumoto, K. Neishi*,
H. Itoh, H. Miyoshi, H. Sato, S. Hosaka,
and J. Koike* |
14:40
-15:00
(9-5) |
The Properties of Cu-In Alloy on Porous SiOCH
for Advanced Copper Metallization [National
Cheng Kung Univ., *United Microelectronics
Corporaiton] D.-C. Perng, K.-C. Hsu, J.-B.
Yeh, and C. Huang* |
15:00
-15:20
(9-6) |
Selective formation of a SnO2 cap layer,
its growth behavior, and oxidation resistance
[Tohoku Univ.] Y. Fujii, Y. Sutou, K. Neishi,
and J. Koike |
| (Coffee Break 20min) |
Session 10: Interconnect performance and
reliability
Chairpersons H. Shibata, K. Ueno |
15:40
-16:10
(10-1) |
Invited: Large-Scale Statistical Evaluation of Early
Failure and Short-Length Effects in Cu Electromigration
[Freescale Semiconductor] M. Gall, M. Hauschildt,
R. Hernandez |
16:10
-16:30
(10-2) |
Ru Barrier Cu / Low-k Interconnect Technology
with Highly-Reliable TDDB and Low Inter-layer
Metal Dielectric Capacitance [Semiconductor
Leading Edge Technologies] Y. Takigawa, N.
Tarumi, M. Shiohara, E. Soda, and S. Ogawa |
16:30
-16:50
(10-3) |
Novel Statistical Analysis of TDDB Lifetime
in Cu/low-k Interconnects by Incorporation
of Overlay Error Model [NEC Electronics]
S. Yokogawa, and H. Tsuchiya |
16:50
-17:10
(10-4) |
Performance of Cu dual-damascene interconnects
using a thin Ti-based self-formed barrier
layer for 28-nm node and beyond [Renesas
Technology, *Kyoto Univ., **The Ritsumeikan
Trust, ***Kobe Steel] K. Ohmori, K. Mori,
K. Maekawa, K. Kohama*, K. Ito*, T. Ohnishi***,
M. Mizuno***, K. Asai, M. Murakami**, and
H. Miyatake |
17:10
-17:30
(10-5) |
A study on Resistivity Increase of Copper
Interconnects with the Dimension Comparable
to Electron Mean Free Path Utilizing Monte
Carlo Simulation [Toshiba] M. Wada, T. Kurusu,
Y. Akimoto, N. Matsunaga, H. Tanimoto, N.
Aoki, Y. Toyoshima, and H. Shibata |
17:30
-17:40 |
Closing Remarks: K. Ueno [Shibaura Institute of Technology] |
|
