{"id":204,"date":"2023-03-24T12:52:11","date_gmt":"2023-03-24T03:52:11","guid":{"rendered":"https:\/\/www.admeta.org\/wp2023\/?post_type=cpt_admeta&p=204"},"modified":"2023-09-29T15:45:53","modified_gmt":"2023-09-29T06:45:53","slug":"invited-2023-en","status":"publish","type":"cpt_admeta","link":"https:\/\/www.admeta.org\/2023\/en\/cpt_admeta\/invited-2023-en","title":{"rendered":"2023-7-en-Invited Speakers"},"content":{"rendered":"
\r\n

<\/span><\/p>\r\n

Plenary Speakers (on-site lecture)<\/b><\/span><\/b><\/h1>\r\n
\r\n
\r\n

PL-1: Interconnect Past, Present and Future<\/span><\/strong><\/span><\/p>\r\n

Prof. Krishna Saraswat
<\/strong>Stanford University<\/strong><\/span><\/p>\r\n

\"\"<\/p>\r\n

Prof. Saraswat received his B.E. degree in Electronics in 1968 from the Birla Institute of Technology and Science, Pilani, India, and his M.S. and Ph.D. degrees in Electrical Engineering in 1969 and 1974 respectively from Stanford University, Stanford, CA. Professor Saraswat stayed at Stanford as a researcher and was appointed Professor of Electrical Engineering in 1983. He also has an honorary appointment of an Adjunct Professor at the Birla Institute of Technology and Science, Pilani, India since January 2004 and a Visiting Professor during the summer of 2007 at IIT Bombay, India. During 2000-2007 he was Associate Director of the NSF\/SRC Center for Environmentally Benign Semiconductor Manufacturing. He has been a technical advisor, board member and consultant to several industrial organizations in USA, Asia and Europe. He has also advised several academic and government organizations world wide. Prof. Saraswat has supervised more than 90 doctoral students, 40 research scholars and has authored or co-authored 15 patents and over 800 technical papers, of which 10 have received Best Paper Award. He is a Life Fellow of the IEEE. He received the Thomas Callinan Award from The Electrochemical Society in 2000 for his contributions to the dielectric science and technology, the 2004 IEEE Andrew Grove Award for seminal contributions to silicon process technology, Inventor Recognition Award from MARCO\/FCRP in 2007, the Technovisionary Award from the India Semiconductor Association in 2007, BITS Pilani Distinguished Alumnus Awards in 2012, the Semiconductor Industry Association (SIA) Researcher of the Year Award in 2012, and the Semiconductor Research Corporatin (SRC) Aristotle Award in 2021. He is listed by ISI as one of the Highly Cited Authors in his field.
<\/span><\/p>\r\n

 <\/p>\r\n

PL-2: Interconnect for the next 10 years: trends, inflection points and future options<\/span><\/strong><\/span><\/p>\r\n

\r\n

Dr. Zsolt Tokei
imec<\/span><\/span><\/strong><\/span><\/p>\r\n

\"\"<\/p>\r\n

Zsolt Tokei is imec fellow, program director nano-interconnects at imec. He joined imec in 1999 and since then held various technical positions in the organization. First as a process engineer and researcher in the field of copper low-k interconnects, then he headed the metal section. Later he became principal scientist, program director nano-interconnects and imec fellow. He earned a M.S. (1994) in physics from the University Kossuth in Debrecen, Hungary. In the framework of a co-directed thesis between the Hungarian University Kossuth and the French University Aix Marseille-III, he obtained his PhD (1997) in physics and materials science. In 1998 he started working at the Max-Planck Institute of D\u00fcsseldorf, Germany, as a post-doctorate researcher. After joining imec, he continued working on a range of interconnect issues including scaling, metallization, electrical characterization, module integration, reliability and system aspects.<\/span><\/p>\r\n<\/div>\r\n<\/div>\r\n

 <\/p>\r\n

\r\n
PL-3: <\/b><\/span>Chiplet<\/b><\/span><\/span> and Advanced Packaging Technologies for HPC and AI<\/b><\/span><\/span><\/span><\/div>\r\n

Dr. Dale McHerron
IBM<\/span><\/strong><\/p>\r\n

\"\"<\/p>\r\n

Dale is currently Senior Manager and Senior Technical Staff Member at IBM Research based in Albany, NY with responsibility for IBM\u2019s Heterogeneous Integration Research Program and project leader in the IBM AI Hardware Research Center.\u00a0 Over his 30 + year career at IBM, Dale has held various technical, managerial, and business development positions in both advanced packaging and CMOS logic R&D.\u00a0 In 2007, he transitioned to the IBM Albany Research lab where he has initiated and led research projects in logic scaling, heterogeneous integration, and has played a key role developing the IBM collaborative research ecosystem in Albany.\u00a0 Dale received his PhD in Chemical Engineering from Virginia Tech with a focus on polymeric materials.\u00a0 Dale has co authored numerous research papers and holds multiple patents in the field of microelectronics.<\/span><\/p>\r\n

\u00a0<\/div>\r\n

Invited Speakers (on-site lecture)<\/b><\/span><\/p>\r\n

Fully Subtractive Ru Topvia as Post-Cu Alternative Metal Interconnects<\/span>
Dr. Koichi Motoyama (IBM Research)<\/span><\/p>\r\n

Advanced Logic Process Technologies toward 2nm and Beyond<\/span>
Dr. Tomonari Yamamoto (Tokyo Electron Ltd.)<\/span><\/p>\r\n

Materials to Systems Co-opitimization (MSCOTM<\/sup>) Platform & its Application towards Next Generation Advanced Interconnect Development for Logic Nodes<\/span> <\/span>
Dr. Ashish Pal (Applied Materials Inc.)<\/span><\/p>\r\n

CMP Process Technology for 3D Flash Memory<\/span>
Dr. Yumiko Kataoka (KIOXIA Corporation)<\/span><\/p>\r\n

Advances In Dielectric Based Wafer to Wafer Bonding<\/span>
Dr. Lan Peng (IMEC)<\/span><\/p>\r\n

Development of Precursors for Area Selective Deposition<\/span>
Dr. Kouhei Iwanaga (Tosoh Corporation)<\/span><\/p>\r\n

Contact Resistance in Vertically Stacked Nanosheet FETs for Sub-3-nm Technology Node<\/span>
Prof. Hyun-Yong Yu (Korea University)<\/span><\/p>\r\n

Boosting Chip Connectivity through Advanced Packaging and BEOL Integration<\/span>
Prof. Huaqiang Wu (Tsinghua University)<\/span><\/p>\r\n

Plasma Etching Technology Next Milestone of Assurance Energy and Environment<\/span>
Prof. Kenji Ishikawa (Nagoya University)<\/span><\/p>\r\n

Interconnections in Advanced Semiconductor Packaging<\/span>
Prof. Katsuaki Suganuma (Osaka University)<\/span><\/p>\r\n<\/div>\r\n<\/div>\r\n<\/div>","protected":false},"featured_media":0,"template":"","txo_year":[30],"class_list":["post-204","cpt_admeta","type-cpt_admeta","status-publish","hentry","txo_year-30"],"aioseo_notices":[],"_links":{"self":[{"href":"https:\/\/www.admeta.org\/2023\/wp-json\/wp\/v2\/cpt_admeta\/204","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.admeta.org\/2023\/wp-json\/wp\/v2\/cpt_admeta"}],"about":[{"href":"https:\/\/www.admeta.org\/2023\/wp-json\/wp\/v2\/types\/cpt_admeta"}],"wp:attachment":[{"href":"https:\/\/www.admeta.org\/2023\/wp-json\/wp\/v2\/media?parent=204"}],"wp:term":[{"taxonomy":"txo_year","embeddable":true,"href":"https:\/\/www.admeta.org\/2023\/wp-json\/wp\/v2\/txo_year?post=204"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}